First-In-First-Out (FIFO) memory devices are widely used to store data. FIFO memory devices generally include one or more FIFO memory blocks. In a FIFO memory block, data generally is stored in a sequential order as data is written into the memory block. The FIFO memory block typically is sequentially read in the same order as it was written. Thus, the data that is first written into the FIFO device is also the data that is first read from the FIFO device.
FIFO memory devices are widely used to buffer data in network applications. In network applications, data packets may be stored in the FIFO memory device in the sequential order that they are written. For routing or distribution, the data is sequentially read starting from the first data that was written.
A plurality of FIFO memory blocks may be used in a FIFO memory device that interfaces a plurality of ports to a data receiving device. For example, an integrated circuit 4-Port Multliplexer-FIFO is marketed by Integrated Device Technology, Inc., the assignee of the present application, as Device IDT77305. See the Data Sheet entitled "UtopiaFIFO.TM. 4-Port (128.times.9.times.4) Multiplexer-FIFO", IDT77305, January 1996. The IDT77305 is a high-speed, low power 4:1 multiplexed FIFO with multiple programmable modes of operation. Within the IDT77305, the input FIFOs act as intermediate queues for the input streams, to allow synchronization with a common output stream. A round robin sequencer sequentially selects one of four FIFOs to output data.
As described above, FIFO memory devices may be used to interface a plurality of ports to a data receiving device. One important application of FIFO memory devices is under a specification known as the Universal Test and Operation Physical (PHY) Interface for Asynchronous Transfer Mode (ATM) specification or the UTOPIA specification. The UTOPIA specification defines an interface between a plurality of ports and an ATM device. In this application, the FIFO memory device synchronizes input and output of data between relatively slow physical devices and a relatively high speed ATM device.
UTOPIA is a Physical Layer to ATM Layer interface that was standardized by the ATM Forum. It has separate transmit and receive channels and specific handshaking protocols. UTOPIA Level 2 includes dedicated address signals for both the transmit and receive directions that allow the ATM Layer device to specify which of the four physical (PHY) channels it is communicating with. In contrast, UTOPIA Level 1 does not use address signals. Instead, key handshaking signals are duplicated so that each channel has its own signals.
In UTOPIA Level 1 operation, it may be desirable to efficiently select which of the four channels, also referred to as ports, communicates with the ATM device. Since UTOPIA Level 1 does not use addressing, the ATM device can enable communications from multiple ports. Since it is possible for more than one port to contain data, it may be desirable to allow only one of the enabled ports to be selected at any time. The selection should preferably allow efficient communications between the relatively low speed ports and the relatively high speed data receiving device.
As described above, it is known to provide a round robin sequencer in order to allow multiple ports to sequentially communicate with the data receiving device. See also, U.S. patent application Ser. No. 08/664,873, filed Jun. 17, 1996 to Chan et al., entitled "First-In-First-Out Memory Device With Programmable Cell Sizes and Multiplexing Functions", assigned to the assignee of the present application, the disclosure of which is hereby incorporated herein by reference. Notwithstanding the use of round robin sequencers to allow multiple ports to communicate data to a data receiving device, there continues to be a need to efficiently interface a plurality of ports to a data receiving device.